Computer chip manufacturing processes typically include the formation of p-n junctions in a semiconductor substrate which are connected by polysilicon which is deposited, masked, and etched to form a patterned polysilicon surface. The patterned polysilicon surface connects with the p-n junctions so as to form numerous semiconductor devices on the semiconductor substrate. Typically, one or more layers of dielectric is then deposited over the surface of the semiconductor. The dielectric is then masked and etched to expose portions of the polysilicon surface through openings which are commonly referred to as vias. A layer of metal or "first metal" is then deposited over the surface of the semiconductor substrate. Typically aluminum is used since it is easy to deposit and form and since it has good conductivity. The metal overlies the layer of dielectric and fills the vias so as to form contacts or "plugs" that make contact between the metal layer and the polysilicon layer so as to allow for contact between the first metal layer and the semiconductor devices. The first metal layer is then masked and etched so as to form metal lines or "interconnects" which connect to the various semiconductor devices by the plugs. Alternate layers of dielectric and metal are then formed over the first metal layer to complete the semiconductor device.
Anti-fuses are structures which selectively allow for electrical contact between electrical circuits. Anti-fuses are typically formed within semiconductor devices to selectively allow for connection to electronic circuits located within the semiconductor device. This allows for easy programming of discrete functions and processes which may be selectively engaged by activating one or more anti-fuses. Anti-fuses in semiconductor devices are typically activated by running a voltage equal to or greater than the threshold voltage and a threshold amount of current to an anti-fuse structure. The voltage and current causes electron migration such that electrical contact is made within the fuse. Once a fuse is activated, the fuse stays open.
Anti-fuses are typically formed between metal layers in semiconductor devices. Thus, special process steps must be added to the semiconductor manufacturing process in order to form anti-fuses between metal layers.
Recent prior art anti-fuses and methods for forming anti-fuses are expensive due to the number of process steps involved. In prior art anti-fuse formation techniques, a dielectric layer which is typically an oxide, commonly referred to as an Inter Metal Oxide (IMO) is deposited over the semiconductor surface. Prior art FIG. 1A shows semiconductor substrate 101 after oxide layer 106 has been deposited over first metal layer 105. Typically, first metal layer 105 is connected to semiconductor devices formed within the semiconductor substrate which include gates such as gates 102-103 by metal plugs such as metal plug 104.
Metal layer 107 is then deposited over dielectric layer 106 as shown in prior art FIG. 1B. Metal layer 107 is then masked and etched to form a strap. Prior art FIG. 1C shows semiconductor device 120 after mask and etch steps have formed strap 108. A layer of amorphous silicon is then deposited. Prior art FIG. 1D shows the structure of prior art FIG. 1C after the deposition of layer of amorphous silicon 109 thereover.
A second mask and etch step is then performed to form an amorphous silicon block. Amorphous silicon block 110 overlies strap 108 as shown in prior art FIG. 1E. An oxide layer oxide layer is then deposited. With reference to prior art FIG. 1F, it can be seen that oxide layer 111 is deposited such that it overlies silicon block 110 and such that it overlies strap 108 and portions of dielectric layer 106.
A third mask and etch process is performed. Prior art FIG. 1G shows the structure of prior art FIG. 1F after masking and etching process steps have formed opening 112 and opening 113 within oxide layer 111. Opening 112 exposes portions of the top surface of amorphous silicon block 110 and opening 113 exposes portions of the top surface of strap 108.
A metal layer is then deposited over the semiconductor surface. FIG. 1H shows the structure of prior art FIG. 1G after deposition of metal layer 114. Metal layer 114 fills openings 112-113 and it overlies the top surface of oxide layer 111.
The metal layer is masked and etched. As shown in prior art FIG. 1I, the mask and etch steps remove some of metal layer 114 shown in prior art FIG. 1H so as to form interconnect 115 and interconnect 116. Interconnect 116 overlies strap 108 so as to electrically connect interconnect 116 to strap 108. Interconnect 115 overlies amorphous silicon block 110 such that amorphous silicon block 110 is disposed between strap 108 and interconnect 115.
Upon applying a sufficient amount of voltage and current between interconnect 115 and interconnect 116, electrons will migrate through amorphous silicon block 110. This migration process generates heat and causes some of the titanium tungsten metal to migrate from strap 108 so as to form an electrical connection between strap 108 and interconnect 115.
Anti-fuse fabrication processes are expensive and the manufacturing process is time consuming due to the number of complex steps of the fabrication process. Moreover, the deposition, mask and etch process increase the number of defects in the manufacturing process, thereby decreasing yield. The numerous deposition, mask and etch steps also take up a significant amount of time so as to cause low throughput rates.
Thus, a need exists for a anti-fuse structure and a method for forming an anti-fuse structure which is easy to manufacture. A further need exists for an anti-fuse structure and a method for forming an anti-fuse structure which minimizes fab process time and which allows for the less expensive manufacture of anti-fuse structures. Moreover, an anti-fuse structure and a method for forming an anti-fuse structure is needed that will increase yield and throughput of manufacturing. The present invention meets the above needs.